Senior ASIC Verification Engineer

Meet the Team

It used to be that high-speed packet forwarding was performed in dedicated ASIC designs. These days we are looking to make those ASICs more general and programmable. [Employer hidden — sign up to reveal] Common ASIC Group is looking for a Senior ASIC Verification Engineer to drive existing projects and engage in new development of our next generation switching systems.

As part of the ASIC team, you will be developing the ASICs at the heart of each of these switch products. There are only a very few teams worldwide that implement such devices. Every time you access the Internet, chances are, your data's been through one of our switches.

Our group is responsible for working on the Silicon One family of chips, where we build some of the most complex ASIC chips using cutting-edge technologies and the latest industry tools and techniques. At [Employer hidden — sign up to reveal], we are at the forefront of innovation in chip design, presenting our engineers with challenging tasks that foster professional growth and career development in this field

Your Impact

You are a talented, motivated ASIC verification engineer ready to contribute to the verification of very complex ASICs. You will have a Design Verification background, hands-on experience in System Verilog and UVM methodology, with in-depth knowledge of C++, scripting, as well as ASIC design and verification flow.

You’ll be part of [Employer hidden — sign up to reveal] Common ASIC Group, focusing on developing and upgrading various test benches and contributing to different aspects of verification infrastructure.

You will collaborate closely with the design team and the hardware team to verify the ASIC in simulation, in emulation and during ASIC bring up.

Responsibilities Include:

• Creating block level test benches including components like drivers/monitors/sequences
• Maintaining existing test benches for block level and/or cluster level
• Upgrading test benches to accommodate new features
• End-to-end verification of various design blocks
• Developing test plans, cover points
• Upgrading/updating configuration/reset sequences (APIs)
• Collaboration with designers/verification engineers to perform cross-block verification
• Writing tests, and debugging regressions
• Contributing to top level verification
• Be a part of emulation testing efforts

Minimum Qualifications:

• Completed degree in Electrical or Computer engineering and at least 8 years of experience in Design Verification
• Proficient in System Verilog /Assertions and UVM
• Proficient in functional coverage and constrained random design verification environments
• Can develop a design verification testbench from scratch.
• Scripting experience (Python, Perl, shell programming)

Preferred Qualifications:

• Knowledge of programming languages (C/C++).
• Familiarity with code database tools like: Perforce/Git.
• Experience with Formal Verification.
• Experience with Emulation.

Why [Employer hidden — sign up to reveal]?

At [Employer hidden — sign up to reveal], we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are [Employer hidden — sign up to reveal], and our power starts with you.