Meet the Team

Step into [Employer hidden — sign up to reveal]'s ASIC Physical Design Team, where innovation meets collaboration. As a group of highly skilled engineers, we're redefining what's possible in silicon technology. Our mission is to drive the future of chip design, managing full chip physical implementation from RTL to GDSII and beyond. Working hand-in-hand with Front-End teams, we transform cutting-edge designs into industry-leading silicon solutions. Here, you'll have the opportunity to shape tomorrow's technology, driving advancements in power, performance, and reliability with every project. Together, we're building the foundation for the future of connectivity.

Your Impact

In this role, you'll drive [Employer hidden — sign up to reveal]'s silicon innovation by creating breakthrough solutions that blend hardware and software. You'll solve complex challenges, accelerate design processes, and deliver impactful technology. Beyond your technical work, you'll be part of a culture that values mentorship, celebrates success, and supports your growth.

• You will be responsible for macro level RTL to GDS implementation and signoff.
• Work with Front-End teams to understand the design architecture to ensure optimal physical implementation.
• Execute physical design tasks, including gate-level netlist synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), and routing.
• Optimize designs to achieve industry-leading power, performance, and area (PPA) metrics while maintaining design integrity through formal verification.
• Conduct Static Timing Analysis (STA), physical verification, formal verification and signoff closure to ensure high-quality results.
• Analyze and resolve Electromigration (EM) and IR-drop (IR) issues, meeting stringent signoff requirements for reliability and performance.

Minimum Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.
• Minimum of 3 years of experience in ASIC design and verification.
• Knowledge of block-level synthesis, place-and-route (PnR), and timing closure.
• First-hand experience with industry-standard PnR and signoff tools such as Synopsys and Cadence.

Preferred Qualifications

• Understanding of all aspects of physical design construction, integration, and methodologies.
• Proficiency in Physical Design Verification, including techniques like LVS and DRC.
• Experience with physical design EDA tools and workflows.
• Expertise in Static Timing Analysis (STA), timing closure, and design constraints.
• Proficiency in scripting languages like Tcl, Python, or Perl, with a focus on automation and efficiency improvements.

Why [Employer hidden — sign up to reveal]?

At [Employer hidden — sign up to reveal], we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are [Employer hidden — sign up to reveal], and our power starts with you.