CAD Physical Design Engineer

🔒 Confidential Employer
Posted 8 May 2026
LOCATION
Not specified
TYPE
Full-time
LEVEL
Mid-Senior level
CATEGORY
Engineering
This employer holds a UK Home Office sponsor license — sponsorship for this specific role is at the employer’s discretion

SKILLS

Physical Design Static Timing Analysis (STA) Place and Route (PnR) Physical Verification Formal Verification EDA Tools RTL-to-GDS Flow Timing Closure

FULL DESCRIPTION

CAD Physical Design Engineer

Company: [Employer hidden — sign up to reveal]
Location: Not specified
Work Type: On-site
Job Type: Full-time
Experience Level: Mid-Senior level

Meet the team

You’ll join the CAD Physical Design team within [Employer hidden — sign up to reveal] Silicon One, responsible for end-to-end backend methodology and flow development from RTL to GDS. This team plays a vital role in delivering high-quality VLSI designs and enabling advanced silicon innovation. Our design center brings together experts across silicon hardware and software, encouraging a collaborative environment passionate about technical excellence and continuous improvement.

Your impact

As a member of our team, you’ll help shape and enhance signoff and implementation flows that support the delivery of high-performance, large-scale, and highly complex devices. Your work will directly contribute to pushing the boundaries of modern chip design.

  • Develop, maintain, and improve backend methodologies and flows from RTL to GDS to enable robust, high-quality VLSI designs.
  • Contribute to the evolution of signoff flows, including physical synthesis, place and route, power optimization, timing closure, and physical closure.
  • Collaborate closely with multi-functional engineering teams to support and improve implementation tool flows.
  • Work with advanced silicon technologies and process nodes to deliver reliable, ground breaking designs.

Minimum qualifications

We are looking for a CAD Physical Design Engineer with 8+ years of experience in Physical Design CAD with strong PnR and STA expertise, or a Design Engineer with solid backend design experience.

  • B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field.
  • Strong understanding of Static Timing Analysis (STA) flows.
  • Familiarity with place and route (PnR), physical verification (PV), and formal verification (FV).
  • Hands-on experience with Physical Design CAD using industry-standard EDA tools (e.g., Synopsys, Cadence).

Preferred qualifications

  • Ability to work optimally both independently and as part of a collaborative team.
  • Strong self-learning attitude with clear and effective communication skills.

Why [Employer hidden — sign up to reveal]?

At [Employer hidden — sign up to reveal], we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are [Employer hidden — sign up to reveal], and our power starts with you.

[Employer hidden — sign up to reveal] is an equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis.

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