Mixed Signal Modelling and Verification Engineer

Main Responsibilities

• Leadership of mixed signal verification activities, including resource planning, task assignment and reporting through to the delivery of thoroughly verified ICs.
• Definition of IC verification strategy for complex mixed signal systems. Including modelling and selection of appropriate simulation techniques and environments.
• Development of reliable and reusable mixed signal testbenches, compliant with industry standard verification techniques, for complex subsystems and mixed signal ICs.
• Develop behavioural models using advanced modelling techniques including real number modelling, user-defined types and Verilog AMS.
• Tool and methodology support for other Engineers working on mixed signal verification activities.
• Hands-on project verification involvement, including testbench development, modelling of analog systems, netlisting and simulation.
• Mentorship and support of other engineers to develop their skills and improve the verification practices within the team.
• Collaboration with other Engineering disciplines to maximize efficiency of development activities.

Required Skills and Qualifications

• BEng / BSc / MEng / MSc Degree or equivalent in Electronics/Computer Science or other related discipline.
• Proven track record in delivering 1st time success with complex mixed signal IC’s.
• Experience of mixed signal simulation techniques and tools, including Spectre, AMS and Digital simulation.
• Knowledge of SystemVerilog
• Experience of analog and digital design.
• Modelling of Analog subsystems using System Verilog and VerilogA/AMS.
• Strong ability to interpret results and resolve problems.
• Highly developed communication skills.
• An innovative, creative, lateral thinking problem solver.

Preferred Skills and Qualifications

• Scripting experience with Python, sh/csh, TCL, Make
• Object orientated programming (OOP) - Use of OOP design patterns
• Knowledge of SVA (SystemVerilog Assertions)
• Metric driven verification - verification planning, requirements extraction - Directed and constrained random verification
• Functional and code coverage analysis
• Power aware verification (using CPF/UPF)
• Testbench design with verification frameworks like UVM

This position is based in either our Edinburgh - UK office, or Newbury -UK office. This is a hybrid remote position and will follow a minimum 2+ day in-office work schedule. [Employer hidden — sign up to reveal] is unable to sponsor or obtain export licenses for this role.