GPU Electrical Analysis Engineer

🔒 Confidential Employer
Posted 22 March 2026
LOCATION
Cambridge
TYPE
Full-time
LEVEL
Mid-Senior level
CATEGORY
Technology
This employer holds a UK Home Office sponsor license — sponsorship for this specific role is at the employer’s discretion

SKILLS

Power Integrity EM Analysis ESD Analysis Power Delivery Networks Power Switches ASIC Integration Circuit Design SPICE Simulation

FULL DESCRIPTION

Posted: 19 Mar 2026

Role Number:200644838-1251

Summary

Posted: 19 Mar 2026

Role Number:200644838-1251

Description

As a GPU Electrical Analysis engineer, you will work closely with the Physical Design team to design power grid specification that achieves the best balance between power integrity targets and PNR performance, power and Area (PPA). You will be involved with the definition of on-die power switch topology, wake-up schemes, and in-rush control. Collaboration with internal teams to drive bump map, custom RDL routing, and package design/optimization will be required. You will develop test structures, procedures/automation, and analysis methodologies for electrical analysis challenges. You will perform Power Integrity, EM, and ESD analysis, drive feedback, and recommend design solutions. Finally, you will communicate and drive the needs of PD and Electrical Analysis with cross-functional teams that will enable achieving the goals of the back-end design for the project.

Minimum Qualifications

  • Experience planning, implementing, and analyzing power delivery networks.
  • Experience designing and analyzing power delivery schemes with power switches.
  • Experience with Signal/Power Integrity checks including Electromigration, Static IR and Dynamic Voltage drop checks.
  • Experience with global power integrity tool (e.g. Redhawk, Voltus).
  • Minimum BS/MS in EE or similar fields and some years of experience

Preferred Qualifications

  • Experience with on-die high frequency power delivery, and exposure to off-die concepts and models.
  • Experience with bump planning and redistribution layer routing strategies, including methods for working with IO bumps and edge encroachment scenarios.
  • Familiar with ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
  • Background with large SoC designs (>20M gates) with frequencies in excess of 1GHz using innovative technologies.
  • Track record in solving complex PD and cross functional problems, driving results directly and or directing a team of engineers to innovate and execute on world class GPU designs.
  • Circuit design and simulation background a plus, but not required.
  • Experience with global timing verification, SPICE simulation/analysis, and Physical Design Verification Flows.

At [Employer hidden — view at passion-project.co.uk], we’re not all the same. And that’s our greatest strength. We draw on the differences in who we are, what we’ve experienced and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. As a registered Disability Confident employer, we will work with applicants to make any reasonable accommodations. [Employer hidden] will consider for employment all qualified applicants with criminal backgrounds in a manner consistent with applicable law. Learn more

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