Sr. Logical Synthesis Engineer

🔒 Confidential Employer
Posted 3 June 2025
LOCATION
Maidenhead
TYPE
Full-time
LEVEL
Mid-Senior level
CATEGORY
Engineering
This employer holds a UK Home Office sponsor license — sponsorship for this specific role is at the employer’s discretion

SKILLS

Synthesis STA Static Timing Analysis VHDL Verilog Perl TCL Python

FULL DESCRIPTION

Summary

Seeking a Sr. Logical Synthesis Engineer to join the Physical Design / Timing Closure team for projects with GHz freq range and cutting edge technologies. The role involves Synthesis & STA experience on low power node technologies, static timing analysis, and gate level simulations.

Key Responsibilities/Duties

  • You will be part a Physical Design / Timing Closure team for projects with GHz freq range and cutting edge technologies.
  • Hand on Understanding Synthesis & STA Experience on low power node technologies.
  • Experience with sign- off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks
  • Experience with full- chip static timing analysis through tapeout, gate level simulations.
  • Experience with Power Analysis using Power Artist and PTPX
  • Work Experience in Synthesis Constraints development, LINT checks, and CDC checks

Core Requirements/Qualifications/Skills

  • 5 to 8 years of Experience in Synthesis and STA
  • Good understanding of overall design Flow RTL to GDS.
  • Should have worked on several full chip designs both flat and hierarchical designs
  • Knowledge on DFT and Physical design is preferred
  • Expertise in STA tools and flow Synopsys/ Cadence tool experience is preferred
  • Strong knowledge in RTL to Net list handoff to Physical design team Experience
  • Experience with VHDL/Verilog
  • Knowledge on Perl / TCL / Python scripting languages

Key Tasks / Responsibilities

  • You will be part a Physical Design / Timing Closure team for projects with GHz freq range and cutting edge technologies.
  • Hand on Understanding Synthesis & STA Experience on low power node technologies.
  • Experience with sign- off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks
  • Experience with full- chip static timing analysis through tapeout, gate level simulations.
  • Experience with Power Analysis using Power Artist and PTPX
  • Work Experience in Synthesis Constraints development, LINT checks, and CDC checks

Key skills / Background

  • 5 to 8 years of Experience in Synthesis and STA
  • Good understanding of overall design Flow RTL to GDS.
  • Should have worked on several full chip designs both flat and hierarchical designs
  • Knowledge on DFT and Physical design is preferred
  • Expertise in STA tools and flow Synopsys/ Cadence tool experience is preferred
  • Strong knowledge in RTL to Net list handoff to Physical design team Experience
  • Experience with VHDL/Verilog
  • Knowledge on Perl / TCL / Python scripting languages

Personal Skills

  • Excellent communication and interpersonal skills
  • Self motivated
  • Take ownership of problems
  • Creative problem solving
  • Strong and effective presentation skills, able to operate at multiple levels including senior management
  • Team player

We look forward to receiving your application.

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